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Public RTD Deliverables
D1.2 "B5G Wireless Tb/s FEC KPI Requirements and Technology Gap Analysis" [March 2018]
This report determines the FEC performance requirement set for the EPIC project and wireless Tb/s use-cases in general. This report sets the performance targets for the FEC development work in the rest of the project.
Sungkwon Hong, Onur Sahin, Chunxuan Ye and Fengjun Xi; ICTC 2018
Abstract: In this paper, a simple relaxation scheme to reduce the encoding and decoding complexity of polar codes is introduced. Unlike the conventional relaxation schemes, the proposed technique relies on selecting relevant encoding/decoding nodes based on initialized relaxation attribute values and their extension to the remainder of the encoder and decoder stages. We show that the proposed relaxation scheme provides comparable BLER performance to the conventional polar codes by numerical simulations, while having significant complexity reduction.
Abstract: The continuous demands to higher throughput in communications systems, in addition to higher spectral efficiency and lowest signal processing latencies, leads to throughput requirements for the digital baseband signal processing far beyond 100Gbit/s. This is one to two orders of magnitude higher than the tens of Gbit/s targeted in the 5G standardization. At the same time, advances in silicon technology due to shrinking feature sizes and increased performance parameters alone won’t provide the necessary gain, especially in energy efficiency for wireless transceivers, which have tightly constrained power and energy budgets. The focus of this talk lies on channel coding that is a major source of complexity in digital baseband processing. We will highlight implementation challenges for the most advanced channel coding techniques, i.e. Turbo-Codes, LDPC codes and Polar codes, and discuss approaches to tackle these challenges.
Abstract: Presentation on Polar Codes for Terabit/s Data Rates
Rami Klaimi, Charbel Abdel Nour, Catherine Douillard and Joumana Farah; Globecom 2018
Abstract: This paper proposes a new family of recursive systematic convolutional codes, defined in the non-binary domain over different Galois fields GF(q) and intended to be used as component codes for the design of non-binary turbo codes. A general framework for the design of the best codes over different GF(q) is described. The designed codes offer better performance than the non-binary convolutional codes found in the literature. They also outperform their binary counterparts when combined with their corresponding QAM modulation or with lower order modulations.
Rami Klaimi, Charbel Abdel Nour, Catherine Douillard and Joumana Farah, ISTC 2018
Abstract: Following the increasing interest in non-binary coding schemes, turbo codes over different Galois fields have started to be considered recently. While showing improved performance when compared to their binary counterparts, the decoding complexity of this family of codes remains a main obstacle to their adoption in practical applications. In this work, a new low-complexity variant of the Min-Log-MAP algorithm is proposed. Thanks to the introduction of a bubble sorter for the different metrics used in the Min-Log-MAP decoder, the number of required computations is significantly reduced. A reduction by a factor of 6 in the number of additions and compare-select operations can be achieved with only a minor impact on error rate performance. With the use of an appropriate quantization, the resulting decoder paves the way for a future hardware implementation.
Ronald Garzon-Bohorquez, Rami Klaimi, Charbel Abdel Nour and Catherine Douillard; ISTC 2018
Abstract: In this paper, new interleaver design criteria for turbo codes are proposed, targeting the reduction of the corre-lation between component decoders. To go beyond the already known correlation girth maximization, we propose several addi-tional criteria that limit the impact of short correlation cycles and increase code diversity. Two application examples are elaborated, targeting an 8-state binary turbo code and a non-binary turbo code defined over GF(64). The proposed design criteria are shown to improve the error correcting performance of the code, especially in the error floor region.
Stefan Weithoffer, Charbel Abdel Nour, Norbert Wehn, Catherine Douillard, Claude Berrou; ISTC 2018
Abstract: In this paper, we demonstrate how the development of parallel hardware architectures for turbo decoding can be continued to achieve a throughput of more than 100 Gb/s. A new, fully pipelined architecture shows better error correcting performance for high code rates than the fully parallel ap-proaches known from the literature. This is demonstrated by comparing both architectures for a frame size K = 128 LTE turbo code and a frame size K = 128 turbo code with parity puncture constrained interleaving. To the best of our knowledge, an investigation of the error correcting performance at high code rates of fully parallel decoders is missing from the literature. Moreover, place & route results for a case study implementation of the new architecture on 28 nm technology show a throughput of 102:4 Gb/s and an area efficiency of 4:34 Gb/s making it superior to reported implementations of other parallel decoder hardware architectures.
Meng Li, Claude Desset, Andre Bourdoux; ISTC 2018
Abstract: IEEE 802.11ay is the amendment to the 802.11 standard that enables Wi-Fi devices to achieve 100~Gbps using the unlicensed mm-Wave (60~GHz) band at comparable ranges to today's commercial 60~GHz devices based on the 802.11ad standard. In this paper, we propose a full row-based layer LDPC decoder supporting all the coding rates for 802.11ay. Taking the property of the parity check matrix of 802.11ay, combining multiple layers into single layer improves the hardware utilization hence increases the throughput. Frame interleaved scheduling increases the throughput significantly by making best use of each pipeline stage. The decoder is synthesized at both 28~nm and 16~nm CMOS technology. For the 28~nm implementation running at 600~MHz, it achieves a throughput of 67~Gbps for coding rate 13/16 with an average power cinsumption of 323 mW at 4 iterations, yielding energy efficiency of 4.8~pJ/bit and area efficiency of 160~Gbps/sqmm. For 16~nm running at 1~GHz, the decoder achieves a throughput of 114~Gbps with an average power of 319 mW at 4 iterations. This gives an improved energy efficiency of 2.8~pJ/bit and area efficiency of 589~Gbps/sqmm.
Norbert When, Onur Sahi https://www.eucnc.eu/special-sessions/special-session-3
Abstract: The continuous demands on increased spectral efficiency, higher throughput, lower latency and lower energy in communication systems impose large challenges on the baseband processing in wireless communication. This applies in particular to channel coding (Forward Error Correction) that is a core technology component in any digital baseband. Future Beyond- 5G use cases are expected to require wireless data rates in the Terabit/s range in a power envelope in the order of 1-10 Watts. In the past, progress in microelectronic silicon technology driven by Moore’s law was an enabler of large leaps in throughput, lower latency, lower power etc. However, we have reached a point where microelectronics can no more keep pace with the increased requirements from communication systems. In addition, advanced technology nodes imply new challenges such as reliability, power density, cost etc. Thus, channel coding for Beyond-5G systems requires a real cross layer approach, covering information theory, algorithm development, parallel hardware architectures and semiconductor technology. The EPIC project addresses these challenges and aims to develop new Forward Error Correction (FEC) schemes for future Beyond-5G use cases targeting a throughput in the Tb/s range. Focus will be on the most advanced FEC schemes, i.e. Turbo codes, Low Density Parity Check (LDPC) codes and Polar codes
Claus Kestel, Stefan Weithoffer, Norbert Wehn; advances in radio science
Abstract: The increasing demand for fast wireless communications requires sophisticated baseband signal processing. One of the computational intense tasks here is advanced Forward Error Correction (FEC), especially the decoding. Finding efficient hardware implementations for sophisticated FEC decoding algorithms that fulfill throughput demands under strict implementation constraints is an active research topic due to increasing throughput, low latency, and high energy efficiency requirements. This paper focuses on the interesting class of Polar Codes that are currently a hot topic. We present a modular framework to automatically generate and evaluate a wide range of Polar Code decoders, with emphasis on design space exploration for efficient hardware architectures. To demonstrate the efficiency of our framework a very high throughput Soft Cancellation (SCAN) Polar Code decoder is shown that was automatically generated. This decoder is, to the best of our knowledge, the fastest SCAN Polar Code decoder published so far.
Garzón Bohórquez, Ronald; Abdel Nour, Charbel; Douillard, Catherine “IEEE Transactions on Communications volume: PP, Issue: 99”
Abstract: A method to design efficient puncture-constrained interleavers for turbo codes (TCs) is introduced. Resulting TCs profit from a joint optimization of puncturing pattern and interleaver to achieve an improved error rate performance. First, the puncturing pattern is selected based on the constituent code Hamming distance spectrum and on the TC extrinsic information exchange under uniform interleaving. Then, the interleaver function is defined via a layered design process taking account of several design criteria such as minimum span, correlation girth, and puncturing constraints. We show that applying interleaving with a periodic cross connection pattern that can be assimilated to a protograph improves error-correction performance when compared to the state-of-the-art TCs. An application example is elaborated and compared with the long term evolution (LTE) standard: a significant gain in performance can be observed. An additional benefit of the proposed technique resides in the important reduction of the search space for the different interleaver parameters.
Stefan Weithoffer, Matthias Herrmann, Claus Kestel, Norbert Wehn, “IEEE International Workshop on Signal Processing Systems (SiPS)”, October 2017
Abstract: The continuing trend towards higher data rates in wireless communication systems will, in addition to a higher spectral efficiency and lowest signal processing latencies, lead to throughput requirements for the digital baseband signal processing beyond 100 Gbit/s, which is at least one order of magnitude higher than the tens of Gbit/s targeted in the 5G standardization. At the same time, advances in silicon technology due to shrinking feature sizes and increased performance parameters alone won’t provide the necessary gain, especially in energy efficiency for wireless transceivers, which have tightly constrained power and energy budgets. In this paper, we highlight the challenges for wireless digital baseband signal processing beyond 100 Gbit/s and the limitations of today’s architectures. Our focus lies on the channel decoding and MIMO detection, which are major sources of complexity in digital baseband signal processing. We discuss techniques on algorithmic and architectural level, which aim to close this gap. For the first time we show Turbo-Code decoding techniques towards 100 Gbit/s and a complete MIMO receiver beyond 100 Gbit/s in 28 nm technology.