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Assessment in month 18 of the EPIC project
Summary of the context and overall objectives of the project
Wireless communication is a key technology of our information society and there is a continuous demand for higher throughput, higher spectral efficiency, lower latencies, lower power and large scalability on communication systems. This imposes large challenges on the baseband signal processing. Channel coding, or forward error correction (FEC), is a crucial technology component of any digital communication system. FEC provides reliable communication in the face of noise that corrupts the transmitted signal, but does at the expense of decreased information bandwidth and increased implementation complexity.
FEC is a major source of power consumption, silicon area and largely contributes to the overall latency and throughput limitations in baseband signal processing. Beyond-5G use cases are expected to require wireless data rates in the Terabit/s range in a power envelope in the order of 1-10 Watts. In the past, progress in microelectronic silicon technology driven by Moore’s law was an enabler of large leaps in throughput, lower latency, lower power etc. However, we have reached a point where microelectronics can no more keep pace with the increased requirements from communication systems, especially in energy efficiency for wireless transceivers, which have tightly constrained power and energy budgets. The complexity of implementing advanced FEC schemes to operate at Tb/s data rates is a huge challenge. To achieve excellent communications performance, advanced channel coding schemes are mandatory. Turbo-, LDPC-, and Polar Codes are the most advanced channel coding schemes known today that exhibit excellent communications performance. However, this comes at the cost of large implementation challenges, especially when targeting throughput towards 1Tb/s under stringent power constraints.
The EPIC project addresses these challenges and develops an implementation-ready FEC technology for Turbo-, LDPC-, and Polar codes that meets the cost and performance requirements of a variety of potential wireless Tb/s use-cases. EPIC methodology differentiates itself by combining code construction, decoding algorithm design and architecture/implementation in a holistic way so that optimization can be carried out jointly over a larger domain. The primary goals of the project are:
to design and implement next generation Forward-Error-Correction for wireless Tb/s technology and Beyond-5G systems.
to advance state-of-the-art codes and develop the principal channel coding technology for wireless Tb/s technology.
to devise a disruptive FEC design framework to unify algorithmic and implementation domains.
to validate and demonstrate the developed FEC technology in virtual silicon tape-out and provide first-in-class wireless Tb/s FEC chipset architecture block.
to put the scientific excellence and contributions to wireless industry in the domain of B5G standardization and technology development at the centre of the project execution.
EPIC key performance metrics (KPI) are throughput in the order of 1 Tb/s, an energy efficiency of about 1 pJ/bit, and an area efficiency > 0.1 Tb/s/mm2, while meeting the stringent communications and flexibility requirements (in terms of code rates, lengths of codes, etc.) of EPIC use-cases.
Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far
At the beginning of the project a thorough search of leading industry standards, business platforms, and emerging applications resulted in a wide range of Tb/s use cases, that were elaborated in detail: data kiosk, virtual reality, intra-device communication, wireless fronthaul/backhaul, data center, hybrid fiber-wireless network and satellite communication. A comprehensive overview of the state-of-the-art FEC decoding in current wireless communication systems from an architecture and implementation perspective were carried out and corresponding gaps with respect to the EPIC use cases were identified, i.e. KPI performance gaps were detailed for turbo, LDPC and polar codes.
After that, the design spaces for all code classes were spread out and an in-depth exploration of this design space was carried out with regard to the EPIC use case requirements. This design space exploration described all the design parameters related to code structure, decoding algorithms, hardware architectures, and the different constraints dictated by the target application and technology. Then, the most promising combination of parameters and techniques from the design spaces to meet the EPIC requirements were identified with the goal to narrow the huge design space. Since there is no silver bullet that matches all code classes, each code class was treated separately. However, there are some commonalities from an architectural point of view. To achieve very high throughput towards 1Tb/s, extreme high parallelism with reasonable area overhead is mandatory. Hence, heavily pipelined architectures for all three code classes were selected as major parallelism paradigm. For each code class, we identified and extensively described promising codes, code construction techniques and architectural templates to achieve the EPIC goals. First results show that throughputs far beyond 100Gbit/s were achievable in 28nm technology for all three code classes. In the further course of the project architectural optimizations, VHDL implementations and virtual chipset implementation for the different code classes in advanced technology nodes will be carried out.
EPIC already started many dissemination activities. These activities include involvement in standardization efforts, participation in dedicated workshops, organizing of special sessions in various conferences and scientific publications. Two keynotes directly related to EPIC at the ISTC 218, one of the most important conferences on channel coding worldwide, emphasized the importance of the implementation aspects and challenges for high-throughput FEC as pursued by EPIC. As direct result DLR organized in February a workshop on High Throughput Coding in Munich. This workshop was very well attended with 70 participants from the scientific and industrial community. EPIC is also member of the Horizon B5G networking cluster which unites all relevant projects from the EU’s Horizon program.
EPIC had an Advisory board meeting in December 2019. This board consists of highly reputed scientists, who gave very positive feedback on the project progress.
Progress beyond the state of the art, expected results until the end of the project and potential impacts (including the socio-economic impact and the wider societal implications of the project so far)
The demand of reaching up to Tb/s throughputs in wireless systems has already started to manifest itself, which elevates the development of a practical FEC solution to a matter of urgency. EPIC develops a new generation of FEC codes in a manner that will serve as a fundamental enabler of practicable beyond 5G wireless Tb/s solutions.