The EPIC project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No. 760150.
Mission and Motivation
EPIC aims to develop a new generation of Forward-Error-Correction (FEC) codes to enable practical wireless Tb/s link technology corresponding to a 10x 100x throughput improvement over the state-of-the-art (SoA). A further goal is to advance FEC schemes (mainly Turbo,LDPC and Polar codes) to obtain the principal channel codes for beyond-5G (B5G) use-cases. EPIC will validate and demonstrate the developed FEC technology in virtual silicon tape-out and provide a first-in-class wireless Tb/s FEC chipset architecture block. Virtual silicone methodologies proved a less time-consuming process during the development of new designs. EPIC's scientific excellence and worldwide leadership position in the FEC domain will contribute to the European research position and strategy. EPIC will organize throughout its lifespan lectures and tutorials on FEC technology. The EPIC concept comprises a technology roadmap, focusing on its SME partners, with the aim of converting fundamental research outcomes into market opportunities via technology IP generation and standardization contributions, ensured by IPR protection.
The EPIC concept and methodology is shaped by the key finding that routine progress in silicon technology in the next decade will not be sufficient to allow FEC implementations to break the Tb/s barrier. Tb/s FEC will not require only help from silicon technology but also major innovations in FEC algorithm design and implementation domains. The EPIC consortium argues that realization of practical and widely deployable ultra-high speed wireless systems, and the elevation of wireless systems to the speed of optical wireline technologies, fundamentally rely on the underlying error-control performance of the technology. The EPIC project will tackle this challenge by developing a comprehensive FEC design framework by incorporating algorithmic and fundamental research and chipset-level virtual implementations under one framework.